Physical implementation flow of a modern electronic design often starts with the floorplanning or placement stage at which various instances, blocks, cells, etc. are inserted into a layout canvas of the electronic design according to various criteria or rules governing the floorplan or the placement layout. This floorplan or placement layout may then be forwarded to a router to perform, for example, global and detailed routing to complete the physical design. Conventional floorplanners or placement tools are merely concerned with the floorplanning or placement rules and constraints but are not aware of the routing or routability requirements, rules, or constraints or do not have sufficient knowledge therefor and thus may cause various issues or errors during the subsequent routing stage. Some errors may even require a portion of a layout be ripped up and rerouted in order to address certain violations (e.g., design rule violations, etc.) and hence consume unnecessary computational resources and delays the development cycle and thus the time to market.
For example, when inserting a block, a cell (e.g., an intellectual property or IP cell, a parameterized or non-parameterized cell, a custom cell, etc.), or a macro (collectively block hereinafter) into a layer of a floorplan or a placement layout, conventional floorplanner or placement tools merely consider the design rules, constraints, and/or requirements pertaining to the floorplan or placement layout. Some conventional approaches do not or even cannot consider any design rules, constraints, and/or requirements about routing, while some other conventional approaches attempt to address this deficiency by anticipating routability through heuristics without concrete data (e.g., by merely considering global routes, flight lines, etc. that at best indicate the approximate direction of the eventual detail routes without providing any useful electrical and/or geometric information of such eventual detail routes. As a result, there is a greater probability that the resulting floorplan or placement may include some regions that may not provide optimal routing solution or may not even be routable. Some conventional approaches attempt to address this shortcoming by considering some rudimentary information (e.g., metal density distribution estimates, congestion estimates, etc.) during floorplanning or placement while hoping that such rudimentary information would somewhat reduce the burden of the routing engine.
Although these conventional floorplanning or placement approaches may alleviate the workload of the router, these conventional approaches nevertheless fall short due to the imprecise estimates. The advent of advanced nodes further exacerbates the problem with these conventional approaches. For example, when inserting a block, a cell (e.g., an intellectual property or IP cell, a parameterized or non-parameterized cell, a custom cell, etc.), or a macro (collectively block hereinafter) into a layer of a floorplan or a placement layout, conventional floorplanner or placement tools merely consider the design rules, constraints, and/or requirements pertaining to the layer into which the block is to be inserted yet often fail to account for design rules, constraints, and/or requirements pertaining to neighboring layers. With the advanced technology nodes that permit only one routing direction for each layer, these conventional approaches often cause routability issues. As a result, routing a modern electronic designs or routability of an electronic design may be severely affected by the placement of devices in the electronic design.
Another challenge that modern electronic designs often face is caused by the more stringent performance, manufacturing, and/or reliability requirements such as the low power requirements, various electromagnetic interference requirements, intersymbol interference requirements, yield requirements, etc. Modern electronic design flows often check these requirements during the post-route analysis or optimization stage; and failure to meet any of these requirements may result in expensive fixes.
Therefore, there is a need for implementing routing aware placement for an electronic design to address at least the aforementioned shortfalls of conventional approaches.